AMD Zen 6 Review

„Zen 6” (Morpheus) – not just an evolution, but a fundamental architectural overhaul

The smart technology and hardware market is constantly evolving, but the transition to a new generation of microarchitecture is always a significant event. „AMD Zen 6” (codenamed Morpheus) is not just an evolutionary step after „Zen 5” – it is a fundamentally redesigned architecture focused on massive parallel computing, a drastic increase in core count, and the integration of artificial intelligence (AI) directly into the processor core.
While the official consumer launch of the „Ryzen” processors is planned for late 2026 or early 2027 (e.g., during CES 2027) due to industry supply challenges, the server-oriented „EPYC” chips and engineering documents already provide a very clear understanding of the technological leap AMD has prepared. In this review, we will thoroughly examine the key architectural decisions, innovations, and upcoming products of „Zen 6”.

2nm Lithography and New Chiplet Strategy

The „Zen 6” design is based on a complex chiplet architecture, where AMD has implemented a so-called split-node strategy. This allows for optimized manufacturing costs and maximum performance where it is most needed.

TSMC 2nm and 3nm Lithography

• CCD (Core Complex Die): Computing core blocks will be manufactured using the advanced „TSMC 2nm” (N2P) technology. This will ensure significantly better power efficiency and higher clock speeds.
• IOD (I/O Die): The input/output controller transitions to „TSMC 3nm” (N3P) or N4 process. It will integrate an updated DDR5 (and possibly early DDR6) memory controller and PCIe Gen 6 support, doubling data throughput.

12-Core CCD and Cache Memory

One of the biggest changes is AMD’s departure from the 8-core design used since „Zen 3” within a single CCD. In the „Zen 6” architecture, a single CCD will accommodate up to 12 cores. To maintain an optimal memory-to-core ratio, the L3 cache is increased to 48 MB per CCD. As usual, the gaming-oriented X3D models will utilize 3D V-Cache technology, allowing the L3 cache to expand to nearly 300 MB in the most complex configurations.

Internal Core Structure and Instruction Execution

Leaked engineering documents for „Zen 6” reveal that AMD engineers have redefined the core logic itself:

• 8-wide Dispatch Engine: The expanded instruction dispatch engine allows the processor to process more instructions in a single clock cycle. This directly correlates with a higher IPC (Instructions Per Clock) metric.
• Full 512-bit Vector Support: Unlike previous generations where AVX-512 instructions were executed over two 256-bit cycles, „Zen 6” will feature native 512-bit execution, encompassing FP64, FP32, FP16, and BF16 data formats.
• Segmented Integer Schedulers: The documents mention six separate integer scheduler domains. This means that instead of one large block, the processor will have distributed resources, reducing latency and congestion during complex calculations.

Integration of AI Computations Directly Inside the CPU Core

If until now AI tasks were primarily handled by separate NPU (Neural Processing Unit) modules or GPUs, with „Zen 6”, AMD integrates artificial intelligence directly into the central processor.

• Direct FP16 Support: The FP16 (half-precision floating-point) format is the standard for AI inference. The official integration of FP16 execution means that „Zen 6” can process low-precision neural network tasks up to twice as fast without additional NPU intervention.
• Memory Profiling (Memory Profiler IBS): Since AI tasks are highly dependent on memory bandwidth, „Zen 6” provides programmers with new tools (IBS events) that allow real-time tracking of memory latencies and optimization of code execution.

From „Ryzen 10000” for Desktops to 256-Core „EPYC”

The architecture will be adapted across all market segments:

1. Desktops – „Ryzen 10000” (Olympic Ridge): With the new 12-core CCD, flagship models will now feature up to 24 cores (2 CCDs x 12), while budget models will start with 6 or 8 cores.
2. Servers and Data Centers – „EPYC” (Venice): Utilizing compact „Zen 6c” cores, the largest server chips will be able to accommodate up to 256 cores / 512 threads in a single processor. This is particularly relevant for hyperscale cloud service providers.
3. Laptops – APU (Medusa Point): In mobile processors, „Zen 6” cores will be paired with next-generation RDNA graphics and an even more powerful XDNA artificial intelligence engine.

Manufacturing Timelines and Competitive Dynamics

Despite impressive specifications, AMD is not rushing. Due to high DDR5 memory prices and disruptions in the industry supply chain (primarily limited „TSMC 2nm” production capacity), the mass release of „Olympic Ridge” desktop processors has been pushed to late 2026 or CES 2027 (January). The first „Zen 6” chips (in the second half of 2026) will likely reach only priority enterprise and server clients.
This means that consumers will face a long transition period during which „Zen 5” will remain the primary choice, while „Zen 6” will become the high-end (enthusiast) segment.

Industry Analysis and Technical Documents

• Tom’s Hardware (2025–2026): Analysis of the 8-wide dispatch engine and 2nm process node.
• TechPowerUp: Information on the CCD architecture expansion to 12 cores and 48 MB L3 cache.
• Wccftech: Data from AMD Financial Analyst Day regarding „Morpheus” core specifications.
• Ballo, A. et al. (2025): „Comparative Review of Multicore Architectures: Intel, AMD, and ARM in the Modern Computing Era.” (MDPI academic review on energy management optimization).
• IEEE Industry Analysis: Microarchitecture adaptation to process FP16 as a direct response to the „memory wall” problem in AI tasks.